1. Field of the Invention
The present invention generally relates to semiconductor devices and methods of fabricating the same. More particularly, the present invention generally relates to semiconductor devices having a dual stacked MIM capacitor and methods of fabricating the same.
A claim of priority is made to Korean Patent Application No. 2004-7362, filed Feb. 4, 2004, the contents of which are incorporated by reference in their entirety.
2. Description of the Related Art
In general, it is easy to control the capacitance for a Metal-Insulator-Metal (MIM) capacitor, because changes in its capacitance change due to voltage and frequency fluctuations are small as compared to a poly-insulator-poly (PIP) capacitor. Therefore, the MIM capacitor is widely used for Applications, such as an analog to digital (AD) converter, an RF device, a switching capacitor filter, and a CMOS image sensor (CIS).
As semiconductor devices have become highly integrated, a MIM capacitor having a higher capacitance per unit of chip area is required. A semiconductor device having a dual stacked MIM capacitor, wherein the capacitor has a high capacitance per unit of chip area has been proposed.
U.S. Patent Publication No. 2003/0197215 (A1) discloses one method of fabricating a semiconductor device having the dual stacked MIM capacitor.
This method discloses forming a stacked layer having a top metal layer, an intermediate metal layer, and a bottom metal layer. The top metal layer is patterned to form a metal plate associated with a first MIM capacitor, the intermediate metal layer is patterned to form metal plates associated with the first and a second MIM capacitors, and the bottom metal layer is patterned to form a metal plate associated with the second MIM capacitor. A via formed in contact with the patterned intermediate metal layer and at least two vias formed in contact with the patterned top metal layer and the patterned bottom metal layer are formed, wherein the at least two vias are electrically connected to each other.
According to this method, a dual stacked MIM capacitor may be fabricated to ensure a high capacitance per unit of chip area. However, each of the top metal layer, the intermediate metal layer, and the bottom metal layer is patterned using separate photolithography and etching processes. As a result, at least three photomasks are required to pattern these metal layers.